(1) Field of the Invention
This invention relates to an integrated circuit semiconductor device, and more particularly to a method for fabricating an array of memory cells using a blanket silicon nitride (Si.sub.3 N.sub.4) etch-stop layer to form self-aligned contact holes for all landing plug contacts. Another blanket Si.sub.3 N.sub.4 layer is used to etch Si.sub.3 N.sub.4 spacers on bit lines only in selected areas while retaining the Si.sub.3 N.sub.4 as an etch-stop layer elsewhere to prevent the capacitor node contacts from shorting to the bit lines when etching openings for forming the capacitors. This provides greater latitude in photolithographic alignment and in critical dimensions (CD).
(2) Description of the Prior Art
In recent years the number and density of memory cells on the DRAM chip have dramatically increased. The DRAM chip areas on the substrate consist of an array of closely spaced memory cells with address and read/write circuits along the periphery of the chip. Currently in production there are 64 million memory cells on a DRAM chip with minimum feature sizes less than a half micrometer. The individual DRAM cells are formed from a single access transistor, typically a field effect transistor (FET), and a storage capacitor with a node contact to one of the two source/drain areas of the FET. The capacitor is used for storing information in binary form (0's and 1's) as electrical charge, and the second source/drain area is connected to a bit line that is used to read and write information via peripheral circuits on the DRAM chip.
The number of memory cells on a DRAM chip is expected to exceed 1 Gigabit after the year 2000. This increased circuit density has resulted from the downsizing of the individual semiconductor devices (FETs) and the resulting increase in device packing density. The reduction in device minimum feature size is due in part to advances in high resolution photolithography and directional (anisotropic) plasma etching. For example, the minimum feature size is expected to be 0.25 to 0.18 micrometer (um) for the next generation of product. However, as minimum feature sizes decrease, it becomes increasingly more difficult to control the photolithographic alignment within design tolerances and to control the critical dimensions. Misalignment can inadvertently result in etching the underlying insulating layers that can cause electrical shorts between the various electrically conducting elements.
Several methods for making DRAM cells with increased memory cell density have been reported in the literature. One method of making DRAM capacitors is described in U.S. Pat. No. 5,714,401 to Kim et al. in which capacitor bottom electrodes are formed from a patterned conducting layer, and a second conducting layer is conformally deposited and etched back to form a fin-shaped structure under the bottom electrode for increased capacitance. Dai in U.S. Pat. No. 5,670,404 describes a method for making self-aligned bit line contacts on DRAMs using an undoped polysilicon layer as an etch-stop layer. The process uses a planar insulating layer that allows bit lines to be etched without conductive residue between the bit lines. In U.S. Pat. No. 5,763,306 to Tsai a method for making a high-density array of DRAM capacitors utilizing a deep pocket between the bit lines, that also forms the capacitor node contacts is described. Sung in U.S. Pat. No. 5,550,078 describes a method for making self-aligned bit line contacts and capacitor node contacts using a reduced mask set. This improves cell density and reduces manufacturing cost.
Therefore there is still a need in the industry to improve the process for fabricating DRAM devices which relax the need for critical photolithographic alignment and provides better control of critical dimensions (CD), while maintaining a cost-effective manufacturing process.